Memory devices are typically provided as internal storage areas in a computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM (read-only memory), which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of ROM that holds instructions for starting up the computer, typically called a basic input output system (BIOS). Unlike RAM, ROM generally cannot be written to by a user. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by specialized programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased in blocks instead of one byte at a time. A typical Flash memory comprises a memory array, which includes a large number of memory cells. The memory cells of a Flash memory array are typically arranged into a “NOR” architecture (where each cell directly coupled to a bitline) or a “NAND” architecture (where the cells are coupled into “strings” of cells, such that each cell is coupled indirectly to a bitline and requires activation of the other cells of the string for access to a selected cell). Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The data in a cell is determined by the presence or absence of the charge in the floating gate. The cells are usually grouped into sections called “erase blocks.” Each of the cells within an erase block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation. Other types of non-volatile memory include, but are not limited to, Polymer Memory, Ferroelectric Random Access Memory (FeRAM), Ovionics Unified Memory (OUM), and Magnetoresistive Random Access Memory (MRAM).
Many Flash memory devices are utilized with specialized software handling and/or management routines, generally referred to as “drivers.” The Flash memory drivers are executed on the “host,” typically a processor or memory controller, and allow the Flash memory device(s) being utilized to be read from and written to by the host. The drivers also provide a layer of logical abstraction for the host; presenting the Flash memory device as a freely re-writeable general access memory device or mass storage device, such as a hard drive, a floppy disk, or other non-volatile machine-usable storage device. The drivers, as part of the Flash memory device software interface/hardware abstraction, typically also manage the internal operation of the Flash memory device; scheduling erase blocks to be erased, managing bad erase blocks, protecting and unprotecting erase blocks, power loss recovery, and load leveling (also called wear leveling) the Flash memory device.
The driver and/or memory management routines are generally supplied by the Flash memory manufacturer to the end-user or system manufacturer. These driver routines are typically supplied in a source code format or as a linkable library and as such must be compiled into the operating system or overall code executing on the device. Self contained and separately loadable drivers also exist, but are typically not utilized in embedded processor devices.
A problem with utilizing Flash memory devices, particularly in embedded processor or portable battery powered systems, is dealing with potentially intermittent power sources or power availability. As Flash memory is non-volatile, once data is stored it will not be affected by loss of power. However, as data write operations, block erasures, and other internal Flash management operations that store or change data or the operating state of the Flash memory device are generally not single step operations, the Flash memory can be left in an incomplete state by a power loss event. For example, a make directory command requires 43 separate write/erase operations by the driver of a specific Flash memory device to complete. Because of these issues the driver software contains “power loss recovery” routines that sequence the Flash memory device through a power loss recovery cycle to check for such uncompleted operations upon power up, and, if possible, finish or correct them.
The testing of these power loss recovery cycles and drivers routines (herein referred to as the power loss recovery cycle) in prior art Flash memory devices and systems has generally involved randomized power loss testing. In this form of system testing, power is removed from the system at a random point during a selected write, erase, or Flash memory management operation and then is restored, testing the power loss recovery cycle and associated driver routines. The testing of a selected write, erase, or Flash memory management operation is continued in this manner for an indefinite period of time (as much as 2 to 3 days), until an appropriate level of confidence in the power loss recovery cycle is achieved. This approach is problematic in that it is empirically based and cannot completely guarantee even after a large number of testing cycles that an error is not present in the power loss recovery cycle or routines; the true coverage of the test is unknown. This form of testing is also time consuming and requires exhaustive testing or retesting when a section of code or hardware is written or changed to verify its correct operation.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative apparatus and methods of testing Flash memory devices, their driver programs, and power loss recovery cycles.